Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations.
The basic CMOS SRAM cell generally includes two n-type or n-channel (nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional nMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
As transistor scaling trends continue, however, it becomes increasingly difficult to design an SRAM cell that has both adequate static noise margin (SNM), adequate trip voltage (Vtrip), and also can endure read and write operations over the desired operating range of temperature, bias conditions, and process variations. The trip voltage (Vtrip) is essentially a measure of the ability of a cell to be written into, and there is an interdependency between SNM and Vtrip in SRAM cell design. For example, if the pass gate is too strong relative to the drive transistor, SNM is degraded. If the pass gate is too weak relative to the drive transistor, Vtrip is degraded. Also, if the load is too weak relative to the drive transistor, SNM is degraded. Single-sided 4T and 5T SRAM cells (e.g., SS 5T SRAM cells) have also been proposed, but these cells generally suffer from much of the above mentioned compromises including poor data stability, low noise margins, and many other such difficult issues.
Generally, therefore, whatever improves SNM, also degrades Vtrip, and vice versa. With technology scaling to the 45 nm node and beyond, it may no longer be possible to achieve a balance in the relative strengths of the pass gate, drive, and load transistors over the desired range of temperature and bias conditions as well as process variations.
In a standard memory array configuration, only a subset of the cells are addressed in an accessed row. During write operations of a standard differential 6T cell, for example, bias conditions must be such that the unaddressed cells in the accessed row are not subject to upset. Therefore, it may be desirable to lower the array Vdd to reduce power dissipation, but low Vdd reduces the stability of the standard 6T SRAM cells. Similarly, it may be desirable to raise the wordline voltage to improve the SNM margin during write operations; however, the higher wordline voltage may also reduce the stability of the unaddressed cells.
Thus, the current balance in cell design values often involves a trade-off that may translate to a higher incidence of data upsets and/or slower access times during cell read and write operations. In addition, although a relatively small subset of the cells may be addressed at any one time in the standard memory configuration, power is consumed on all cells of the array.
Accordingly, there is a need for an improved SRAM array structure and method of operating the SRAM array in a manner that provides optimum static noise margin, while minimizing data upsets and power dissipation during read and write operations in the fabrication of SRAM memory devices.